As mobile systems and various application systems have been developed, a demand for flash memory is increasing. Flash memory, which is a nonvolatile memory device, can be electrically erased and programmed. Flash memory typically has the characteristic that data can be preserved even in a state where power is not supplied. Furthermore, flash memory typically consumes less power than a storing medium based on magnetic disc memory and has a fast access time like in a hard disc.
Flash memory may be classified into NOR flash memory and NAND flash memory based on the connection state between cells and bitlines. In particular, NAND flash memory has a structure in which at least two cell transistors are connected in series to one bitline, and stores and erases data by using a Fowler-Nordheim (F-N) tunneling method. In general, NOR flash memory consumes relatively large amounts of power and thus may not be advantageous to high integration. However, NOR flash memory has an advantage in that it can be easily used even at high speed applications. NAND flash memory uses a smaller cell current than in NOR flash memory and thus is advantageous in terms of high integration.
Recently, as mobile systems have been developed, a larger capacity of memory devices is required. NAND flash memory is advantageous in terms of high integration and, thus, is being used to meet these requirements. However, there is a limitation in using microprocesses of a semiconductor device as the alternatives for increasing memory capacity.
As one of the alternatives for increasing memory capacity, conventional multi-level cell (MLC) technology has been widely used. In MLC technology, one memory cell is programmed using a plurality of threshold voltages and a plurality of bits of data is stored in the one memory cell. However, in MLC technology, a sufficient margin between the threshold voltages should be secured. Thus, the bit number of data that can be stored in one memory cell may be limited.
As another alternative, a 3D stack structure of semiconductor layers that has been used in a memory device such as dynamic random access memory (DRAM) may be applied to a flash memory device. Furthermore, a decoder for driving a memory cell (i.e., X-decoder or Y-decoder) is shared in the 3D stack structure of semiconductor layers so that a chip size can be reduced. However, when a plurality of semiconductor layers are stacked to implement a NAND flash memory device, if general program, read and erase operations are performed to drive the NAND flash memory device, a disturbance may occur during a program and/or read operation or an undesired soft program may be generated in a memory cell that exists in another memory block during an erase operation in a predetermined memory block.